The present invention relates to a dynamic semiconductor memory device and, more particularly, to an improvement of a word line driver for driving a word line.
In the memory cell of a dynamic semiconductor memory device (DRAM), a bit line voltage is written in a memory capacitor through a transfer gate using an N channel MOS transistor. In the write access, to prevent the high-level voltage on the bit line from lowering by an amount corresponding to the threshold voltage of the transfer gate before being written in the memory capacitor, a signal voltage for driving the transfer gate is boosted to a level higher than the power supply voltage. The gate electrode of the transfer gate is connected to a word line. The high-level voltage on the word line is set at step-up voltage VPP having a value corresponding to (high-level voltage on bit line)+(threshold voltage of N channel MOS transistor)+(margin for process variations) (this scheme will be referred to as a word line boosting scheme).
In a word line driver which applies step-up voltage VPP to one word line selected from a plurality of word lines by a row decoder and applies a low-level voltage to nonselected word lines, step-up voltage VPP is supplied as a power supply voltage and is also supplied as a high-level input signal.
In the word line driver of a DRAM according to the above-mentioned word line boosting scheme, each gate of the P channel and first N channel MOS transistors connected to the word line receives from the row decoder a decode output signal which becomes circuit ground voltage VSS when the word line is to be selected. The source of the P channel MOS transistor receives word line drive signal WDLV which becomes step-up voltage VPP when the word line is to be selected. The gate of the second N channel MOS transistor receives signal /WDLV of regular power supply voltage VDD. The logical level of signal /WDLV is inverted from that of word line drive signal WDLV, and the voltage of the high level of signal /WDLV is smaller than step-up voltage VPP.
In the word line driver having such a circuit arrangement, when the decode output signal from the row decoder is circuit ground voltage VSS in the selected state wherein signal WDLV is step-up voltage VPP, the P channel MOS transistor is turned on, and step-up voltage VPP is output to word line WL. When the decode output signal from the row decoder is VPP in the selected state, the N channel MOS transistor is turned on, and circuit ground voltage VSS is output to word line WL. When the word line driver is in a nonselected state, signal /WDLV becomes VDD. Then, the second N channel MOS transistor is turned on, so that word line WL is held at circuit ground voltage VSS.
As the decoder for decoding an address signal and generating a signal to be supplied to the word line driver on the basis of the decode output signal, there is a level converter based on a dynamic circuit scheme wherein a predetermined circuit node is precharged with step-up voltage VPP and determining the input level of the input signal having an internal circuit voltage level (VDD or VSS).
However, the above-mentioned prior art has the following problems.
(1) The voltage to be applied to the word line is VPP. For this reason, when the stored charges in the memory capacitor are at level "0", and the word line is set at level "1", the step-up voltage is applied to the gate oxide film of the transfer gate, so the reliability of the oxide film is degraded as compared to other logic transistors.
(2) To obtain almost the same reliability as that of other logic transistors for the gate oxide film of the transfer gate, the film must be made thicker to equalize the electric field applied to the gate oxide film, resulting in a decrease in conductance of the transfer gate. This decrease in conductance lowers the speed of the entire DRAM.
(3) It takes a longer time to charge a load capacity such as the capacitance of a word line with the step-up voltage than to charge using the internal power supply voltage. The increase in charge time also lowers the speed of the entire DRAM.
As a technique of avoiding these problems, a negative voltage driven word line scheme disclosed in the below literature is known:
1995 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE; ISSCC95/SESSION 14/DRAM/PAPER FA 14.3, pp 248-249, "Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs", T. Yamada et al.
In this technique, while holding the amplitude of the word line, the voltage level on the low level side is set at a negative potential, i.e., the voltage level on the low level side of the amplitude of the word line signal is lowered, and simultaneously, the threshold voltage of the transfer gate is lowered.
FIG. 11 exemplifies the relationship in voltages between the above word line boosting scheme and the negative voltage driven word line scheme.
The left side illustration in FIG. 11 shows the former word line boosting scheme. The high-level voltage on the word line is set at step-up voltage VPP (e.g., 4.5V), and the low-level voltage is set at circuit ground voltage VSS (0V). High-level voltage VDD of the internal circuit is set at, e.g., 3.3V. Vth in FIG. 11 represents the threshold voltage (e.g., 0.9V) of the transfer gate in the memory cell.
The right side illustration in FIG. 11 shows the latter negative voltage driven word line scheme. Low-level voltage VWLl on the word line is set to be lower (e.g., -0.6V) than circuit ground voltage VSS. High-level voltage VWLh on the word line is set at 3.9V which is lower than step-up voltage VPP by 0.6V. In this scheme, threshold voltage Vth* of the transfer gate in the memory cell is set to be lower than threshold voltage Vth of the word line boosting scheme by (VPP-VWLh).
According to the negative voltage driven word line scheme, when the signal voltage on the word line is at high level, the write voltage for the memory cell capacitor is VWLh-Vth*=VPP-Vth, i.e., equal to the write voltage in the word line boosting scheme. When the signal voltage on the word line is at low level, the charge hold characteristic of the memory cell capacitor is represented by Vth*-VWLl=Vth-VSS, i.e., the same characteristic as that in the word line boosting scheme.
That is, in the negative voltage driven word line scheme, the high-level signal voltage on the word line can be lowered without degrading the write characteristic and charge hold characteristic, so the reliability of the gate oxide film of the transfer gate can be prevented from lowering.
FIG. 4 on page 249 of said literature "ISSCC95/SESSION 14/DRAM/PAPER FA 14.3" exemplifies a prior art word line driver circuit used for a DRAM of the negative voltage driven word line scheme. This circuit comprises a first MOS transistor pair having low threshold voltages, a P channel MOS transistor pair of the Vpp (2.2V) side, and a second N channel MOS transistor pair of the Vbb (-0.5V) side.
In this circuit, the one gate of the first MOS transistor pair is connected to a circuit with a predetermined potential Vcc (1.2V), and the other gate thereof is circuit-grounded. The respective one electrodes (sources or drains) of the MOS transistor pairs of the gate-Vcc side and of the gate-grounded side receive the row decode output.
The Vpp-side MOS transistor pair and the Vbb-side MOS transistor pair have cross-coupled circuit connections. The one drain of the Vpp-side MOS transistor pair is connected to the other electrode (drain or source) of the gate-Vcc side MOS transistor pair, and the one drain of the Vbb-side MOS transistor pair is connected to the other electrode (drain or source) of the gate-grounded side MOS transistor pair. The respective other drains of the Vpp-side MOS transistor pair and the Vbb-side MOS transistor pair are connected to each other at a connection node, and a word line drive signal corresponding to the row decode output is supplied from the connection node to word line WL.
In the word line driver having this arrangement, the output signal from the row decoder is level-converted into a signal having an amplitude between Vpp and Vbb and supplied to word line WL.
However, the word line driver of the above ISSCC95 requires six MOS transistors, i.e., the six MOS transistors must be arranged in units of word lines. This makes a pattern layout of the word line driver according to the decoder pitch difficult. Thus, an increase in occupied area of the driver lowers the cell occupation ratio, resulting in an increase in manufacturing cost.
In addition, since a relatively large voltage of Vpp-Vbb is applied to the gate oxide film of the Vpp-side and Vbb-side MOS transistor pairs in the word line driver, these MOS transistor pairs also have a problem of poor reliability with respect to the withstanding voltage of their gate.